Renesas Develops Write Technologies for Embedded STT-MRAM Reducing MCUs Power Consumption

Announced at IEDM 2021: Confirmed Reduced Power Consumption and Increased Speed in Write Operations on 16 nm FinFET Logic Process Embedded STT-MRAM Test Chip

Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced the development of two technologies that reduce the energy and voltage application time for the write operation of spin-transfer torque magnetic random-access memory (STT-MRAM, hereinafter MRAM). On a 20-megabit (Mbit) test chip with embedded MRAM memory cell array in a 16 nm FinFET logic process, a 72 percent reduction in write energy and a 50 percent reduction in the voltage application time were confirmed. The new technologies are: 1) A self-termination write scheme with slope pulse application, in which the write pulse is automatically and adaptively terminated due to write characteristics of each memory cell; 2) A write sequence to optimize the number of bits, to which write voltage is applied simultaneously. Combined, these technologies make it possible to reduce the power consumption and increase the speed of write operations.